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RT8251 ? ds8251-04 february 2013 www.richtek.com 1 ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. 5a, 24v, 570khz step-down converter applications z distributed power systems z battery charger z dsl modems z pre-regulator for linear regulators general description the RT8251 is a monolithic step-down switch mode converter with a built-in internal power mosfet. it achieves 5a continuous output current over a wide input supply range with excellent load and line regulation. current mode operation provides fast transient response and eases loop stabilization. the RT8251 provides protection functions such as cycle-by-cycle current limiting and thermal shutdown. in shutdown mode, the regulator draws 25 a of supply current. programmable soft-start minimizes the inrush supply current and the output overshoot at initial startup. the RT8251 requires a minimum number of external components. the RT8251 is available in wqfn-16l 3x3 and sop-8 (exposed pad) packages. features z z z z z wide operating input voltage range : 4.75v to 24v z z z z z adjustable output voltage range : 0.8v to 15v z z z z z output current up to 5a z z z z z 25 a low shutdown current z z z z z internal power mosfet : 70m z z z z z high efficiency up to 95% z z z z z 570khz fixed switching frequency z z z z z stable with low esr output ceramic capacitors z z z z z thermal shutdown protection z z z z z cycle-by-cycle over current protection z z z z z rohs compliant and halogen free pin configurations (top view) wqfn-16l 3x3 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 gnd vin vin vin sw sw boot sw fb en comp ss vin vin sw sw gnd 17 sop-8 (exposed pad) comp boot vin sw gnd ss en fb gnd 2 3 4 5 6 7 8 9 RT8251 lead plating system g : green (halogen free and pb free) package type qw : wqfn-16l 3x3 (w-type) sp : sop-8 (exposed pad-option 1)
RT8251 2 ds8251-04 february 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. marking information typical application circuit figure 1. typical application circuit for wqfn-16l 3x3 figure 2. typical application circuit for sop-8 (exposed pad) v out (v) r1 (k ) r2 (k ) r c (k ) c c (nf) l1 ( h) c out ( f) 15 182 10 51 1 22 44 10 115 10 43 1.2 10 44 8 91 10 39 1.5 10 44 5 52.3 10 30 1.5 6.8 44 3.3 30.9 10 22 2.2 4.7 44 2.5 21.5 10 16 2.2 4.7 44 1.8 12.4 10 13 2.2 2.2 44 1.2 4.99 10 13 2.2 2.2 44 table 1. recommended component selection RT8251 en boot fb sw 7 5 10 to 14 9 c out 22f x 2 v out 3.3v/5a gnd ss 8 c ss 10nf 4, exposed pad (17) vin 1, 2, 3, 15, 16 v in 4.75v to 24v comp c c 2.2nf r c 22k c p (open) 6 r1 30.9k r2 10k c boot 100nf d b540c l 4.7h 10f x 2 c in chip enable 3.3v/5a vin en gnd boot fb sw 7 5 2 3 1 l 4.7h 100nf 22f x 2 r1 30.9k r2 10k v out 10f x 2 chip enable v in 4.75v to 24v RT8251 d b540c ss 8 c ss 10nf comp c c 2.2nf r c 22k c p nc 6 4, exposed pad(9) c boot c out c in ge= : product code ymdnn : date code RT8251gqw RT8251gsp : product number ymdnn : date code RT8251gsp RT8251 gspymdnn ge=ym dnn
RT8251 3 ds8251-04 february 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin no. wqfn-16l 3x3 sop-8 (exposed pad) pin name pin function 1, 2, 3, 15, 16 2 vin power input. vin supplies the power to the ic, as well as the step-down converter switches. connect vin with a 4.75v to 24v power source. connect vin to gnd with a capacitor that the capacitance is large enough to eliminate noise on the input to the ic. 4, 17 (exposed pad) 4, 9 (exposed pad) gnd ground. this pin is the voltage reference for the regulated output voltage. for this reason, care must be taken in its layout. this node should be placed outside of the d1 to c in ground path to prevent switching current spikes from inducing voltage noise into the part. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 5 5 fb feedback input. an external resistor divider from the output to gnd, tapped to the fb pin, sets the output voltage. 6 6 comp compensation node. this node is the output of the transconductance error amplifier and the input to the current comparator. frequency compensation is done at this node by connecting a series r-c to ground. 7 7 en enable input. en is a digital input that turns the regulator on or off. drive en higher than 1.4v to turn on the regulator, lower than 0.4v to turn it off. for automatic startup, leave en unconnected. 8 8 ss soft-start control input. ss controls the soft start period. connect a capacitor ( R 10nf) from ss to gnd to set the soft-start period. a 10nf capacitor sets the soft-start period to 1ms. 9 1 boot bootstrap. this capacitor c boot is needed to drive the power switch?s gate above the supply voltage. it is connected between the sw and bs pins to form a floating supply across the power switch driver. the voltage across c boot is about 5v and is supplied by the internal +5v supply when the sw pin voltage is low. 10, 11, 12, 13, 14 3 sw power switching output. sw is the switching node that supplies power to the output. connect the output lc filter from sw to the output load. note that a capacitor is required from sw to boot to power the high-side switch. functional pin description
RT8251 4 ds8251-04 february 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. absolute maximum ratings (note 1) z supply voltage, v in ------------------------------------------------------------------------------------------ ? 0.3v to 26v z switching voltage, v sw ------------------------------------------------------------------------------------- ? 0.3v to (v in + 0.3v) z boot voltage, v boot --------------------------------------------------------------------------------------- (v sw ? 0.3v) to (v sw + 6v) z all other pins ------------------------------------------------------------------------------------------------- ? 0.3v to 6v z power dissipation, p d @ t a = 25 c wqfn-16l 3x3 ----------------------------------------------------------------------------------------------- 1.471w sop-8 (exposed pad) -------------------------------------------------------------------------------------- 1.333w z package thermal resistance (note 2) wqfn-16l 3x3, ja ------------------------------------------------------------------------------------------ 68 c/w wqfn-16l 3x3, jc ----------------------------------------------------------------------------------------- 7.5 c/w sop-8 (exposed pad), ja --------------------------------------------------------------------------------- 75 c/w sop-8 (exposed pad), jc -------------------------------------------------------------------------------- 15 c/w z junction temperature ---------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------ 260 c z storage temperature range ------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) --------------------------------------------------------------------------------- 2kv recommended operating conditions (note 4) z supply voltage, v in ------------------------------------------------------------------------------------------ 4.75v to 24v z enable voltage, v en ----------------------------------------------------------------------------------------- 0v to 5.5v z junction temperature range ------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------- ? 40 c to 85 c function block diagram va + - + - + - uv comparator oscillator 570khz foldback control 0.4v internal regulator + - 1.1v 1a shutdown comparator current sense amplifier boot vin gnd sw fb en comp 3v 10k va v cc v cc slope comp current comparator ss logic + - ea 0.8v gm = 820a/v + 10a v cc
RT8251 5 ds8251-04 february 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit feedback reference voltage v fb 4.75v Q v in Q 24v 0.784 0.8 0.816 v high-side switch-on resistance r ds(on)1 -- 70 -- m low-side switch-on resistance r ds(on)2 -- 15 -- high-side switch leakage v en = 0v, v sw = 0v -- -- 10 a current limit i lim duty = 85%; v boot ? sw = 4.8v -- 6.8 -- a current sense transconductance g cs output current to v comp -- 4.6 -- a/v error amplifier tansconductance gm i c = 10 a -- 920 -- a/v oscillator frequency f sw 420 570 720 khz short circuit oscillation frequency v fb = 0v -- 185 -- khz maximum duty cycle d max v fb = 0.7v -- 85 -- % minimum on-time t on -- 100 -- ns uvlo threshold rising -- 4.1 -- v uvlo threshold hysteresis -- 200 -- mv logic low v il -- -- 0.4 en input voltage logic high v ih 1.4 -- 5.5 v enable pull up current v en = 0v -- 1 -- a shutdown current i shdn v en = 0v -- 25 -- a quiescent current i q v en = 2v, v fb = 1v -- 0.8 1 ma soft-start current i ss v ss = 0v -- 10 -- a soft-start period c ss = 10nf -- 1 -- ms thermal shutdown t sd -- 150 -- c electrical characteristics (v in = 12v, t a = 25 c unless otherwise specified) note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT8251 6 ds8251-04 february 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics output voltag deviation vs. load current -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0.001 0.01 0.1 1 10 load current (a) output voltage deviation (%) 1 v out = 3.3v v in = 24v v in = 12v v in = 5v reference voltage vs. temperature 0.786 0.791 0.796 0.801 0.806 0.811 0.816 -50 -25 0 25 50 75 100 125 temperature ( c) reference voltage (v) v in = 12v output voltage deviation vs. input voltage -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 4 6.5 9 11.5 14 16.5 19 21.5 24 input voltage (v) output voltage deviation (%) 1 v out = 3.3v i out = 5a i out = 3a i out = 0a efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 00.511.522.533.544.55 load current (a) efficiency (%) v in = 12v v out = 3.3v v in = 24v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 load current (a) efficiency(%) v out = 5v v in = 12v v in = 24v quiescent current vs. temperature 0 0.2 0.4 0.6 0.8 1 1.2 -50 -25 0 25 50 75 100 125 temperature ( c) quiescent current (ma ) v in = 12v
RT8251 7 ds8251-04 february 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. load transient response time (100 s/div) i out (2a/div) v out (200mv/div) v in = 12v, v out = 3.3v i out = 0a to 5a load transient response time (100 s/div) i out (2a/div) v out (200mv/div) v in = 12v, v out = 3.3v i out = 2.5a to 5a current limit vs. duty cycle 5.7 6.3 6.9 7.5 8.1 8.7 9.3 0 102030405060708090100 duty cycle (%) peak current (a ) switching frequency vs. input voltage 550 560 570 580 590 600 610 4 6.5 9 11.5 14 16.5 19 21.5 24 input voltage (v) switcing frequency (khz) 1 v out = 3.3v, i out = 1a switching frequency vs. temperature 510 530 550 570 590 610 630 -50 -25 0 25 50 75 100 125 temperature ( c) switching frequenc (khz) 1 11 v out = 3.3v, i out = 1a v in = 12v v in = 24v output ripple time (1 s/div) i sw (2a/div) v out (10mv/div) v in = 12v v out = 3.3v i out = 5a v sw (10v/div)
RT8251 8 ds8251-04 february 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. power on from en time (250 s/div) v out (2v/div) v en (5v/div) v in = 12v, v out = 3.3v, i out = 5a power off from en time (25 s/div) v out (2v/div) v en (5v/div) v in = 12v, v out = 3.3v, i out = 5a
RT8251 9 ds8251-04 february 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information the RT8251 is an asynchronous high voltage buck converter that can support the input voltage range from 4.75v to 24v and the output current can be up to 5a. output voltage setting the resistive divider allows the fb pin to sense the output voltage as shown in figure 3. figure 3. output voltage setting the output voltage is set by an external resistive divider according to the following equation : ?? + ?? ?? out fb r1 v = v1 r2 where v fb is the feedback reference voltage (0.8v typ.). external bootstrap diode connect a 100nf low esr ceramic capacitor between the boot pin and sw pin. this capacitor provides the gate driver voltage for the high side mosfet. it is recommended to add an external bootstrap diode between an external 5v and the boot pin for efficiency improvement when input voltage is lower than 5.5v or duty cycle is higher than 65%. the bootstrap diode can be a low cost one such as 1n4148 or bat54. the external 5v can be a 5v fixed input from system or a 5v output of the RT8251. figure 4. external bootstrap diode soft-start the RT8251 contains an external soft-start clamp that gradually raises the output voltage. the soft-start timming can be set by the external capacitor between ss pin and gnd. the chip provides a 10 a charge current for the external capacitor. if 10nf capacitor is used to set the soft-start time, its period will be 1ms (typ.). chip enable operation the en pin is the chip enable input. pull the en pin low (<0.4v) will shutdown the device. during shutdown mode, the RT8251 quiescent current drops to lower than 25 a. drive the en pin to high ( >1.4v, < 5.5v) will turn on the device again. if the en pin is open, it will be pulled to high by internal circuit. for external timing control (e.g.rc), the en pin can also be externally pulled to high by adding a100k or greater resistor from the vin pin (see figure 5). inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and output voltage. the ripple current i l increases with higher v in and decreases with higher inductance. out out l in vv i = 1 fl v ??? ? ?? ??? ? ??? ? having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. high frequency with small ripple current can achieve highest efficiency operation. however, it requires a large inductor to achieve this goal. for the ripple current selection, the value of i l = 0.24(i max ) will be a reasonable starting point. the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? RT8251 gnd fb r1 r2 v out 5v 100nf RT8251 sw boot the inductor 's current rating (caused a 40 c temperature rising from 25 c ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. please see table 2 for the inductor selection reference.
RT8251 10 ds8251-04 february 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. diode selection when the power switch turns off, the path for the current is through the diode connected between the switch output and ground. this forward biased diode must have a minimum voltage drop and recovery times. schottky diode is recommended and it should be able to handle those current. the reverse voltage rating of the diode should be greater than the maximum input voltage, and current rating should be greater than the maximum load current. for more detail please refer to table 4. c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the high side mosfet. to prevent large ripple current, a low esr input capacitor sized for the maximum rms current should be used. the rms current is given by : this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for the input capacitor, two 10 f low esr ceramic capacitors are recommended. for the recommended capacitor, please refer to table 3 for more detail. the selection of c out is determined by the required esr to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for c out selection to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : the output ripple will be highest at the maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirement. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr value. however, it provides lower capacitance density than other types. although tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr. however, it can be used in cost-sensitive applications for ripple current rating and long term reliability considerations. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr) also begins to charge or discharge c out generating a feedback error signal for the regulator out in rms out(max) in out v v i = i 1 vv ? out l out 1 viesr 8fc ?? ?? + ?? ?? component supplier series dimensions (mm) tdk slf10165 10.1x10.1x7 taiyo yuden nr10050 10x9.8x5 tdk vlf12060 12x11.7x6 table 2. suggested inductors for typical application circuit
RT8251 11 ds8251-04 february 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. emi consideration since parasitic inductance and capacitance effects in pcb circuitry would cause a spike voltage on the sw pin when high-side mosfet is turned-on/off, this spike voltage on sw may impact on emi performance in the system. in order to enhance emi performance, there are two methods to suppress the spike voltage. one is to place an r-c snubber between sw and gnd and make them as close as possible to the sw pin (see figure 5). another method is to add a resistor in series with the bootstrap capacitor, c boot . but this method will decrease the driving capability to the high-side mosfet. it is strongly recommended to reserve the r-c snubber during pcb layout for emi improvement. moreover, reducing the sw trace area and keeping the main power in a small loop will be helpful on emi performance. for detailed pcb layout guide, please refer to the section of layout consideration. figure 5. reference circuit with snubber and enable timing control thermal considerations for continuous operation, do not exceed the maximum operation junction temperature 125 c. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature , t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT8251, the maximum junction temperature is 125 c. the junction to ambient thermal resistance ja is layout dependent. for psop-8 and wqfn packages, the thermal resistance ja are 75 c/w and 68 c/w on the standard jedec 51-7 four-layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (75 c/w) = 1.333w for psop-8 p d(max) = (125 c ? 25 c) / (68 c/w) = 1.471w for wqfn (min.copper area pcb layout) p d(max) = (125 c ? 25 c) / (49 c/w) = 2.04w for psop-8 (70mm 2 copper area pcb layout) the thermal resistance ja of sop-8 (exposed pad) is determined by the package architecture design and the pcb layout design. however, the package architecture design had been designed. if possible, it's useful to increase thermal performance by the pcb layout copper design. the thermal resistance ja can be decreased by adding copper area under the exposed pad of sop-8 (exposed pad) package. as shown in figure 6, the amount of copper area to which the sop-8 (exposed pad) is mounted affects thermal performance. when mounted to the standard vin en gnd boot fb sw 7 5 2 3 1 l 4.7h 100nf 22f x 2 r1 30.9k r2 10k v out 3.3v/5a 10f x 2 chip enable v in 4.75v to 24v RT8251 d b540c ss 8 c ss 10nf comp c c 2.2nf r c 22k c p nc 6 4, exposed pad(9) c boot c out c in r boot * r s * c s * r en * c en * * : optional
RT8251 12 ds8251-04 february 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. sop-8 (exposed pad) pad (figure 6a), ja is 75 c/w. adding copper area of pad under the sop-8 (exposed pad) (figure 6.b) reduces the ja to 64 c/w. even further, increasing the copper area of pad to 70mm 2 (figure 6.e) reduces the ja to 49 c/w. the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT8251 packages, the derating curves in figure 7 and figure 8 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. figure 7. derating curves for psop-8 package 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0 255075100125 ambient temperature p ower di ss i pat i on (w) ( c) copper area 70mm 2 50mm 2 30mm 2 10mm 2 min.layout four layer pcb 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 153045607590105120135 ambient temperature (c) maximum power dissipation (w) 1 four layer pcb wqfn-16l 3x3 figure 8. derating curves for wqfn package (a) copper area = (2.3 x 2.3) mm 2 , ja = 75 c/w (b) copper area = 10mm 2 , ja = 64 c/w (c) copper area = 30mm 2 , ja = 54 c/w (d) copper area = 50mm 2 , ja = 51 c/w (e) copper area = 70mm 2 , ja = 49 c/w figure 6. themal resistance vs. copper area layout design
RT8251 13 ds8251-04 february 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. layout consideration follow the pcb layout guidelines for optimal performance of the RT8251. ` keep the traces of the main current paths as short and wide as possible. ` put the input capacitor as close as possible to the device pins (vin and gnd). ` lx node is with high frequency voltage swing and should be kept at small area. keep analog components away from the lx node to prevent stray capacitive noise pick- up. figure 9. pcb layout guide for wqfn package ` connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the RT8251. ` connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors. ` examples of pcb layout guide are shown in figure 9 and figure 10 for reference. gnd 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 gnd vin vin vin sw sw boot sw fb en comp ss vin vin sw sw gnd 17 c in c out r c c c c p c ss c boot vout vout gnd r1 r2 input capacitor must be placed as close as to the ic as possible. sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace. the feedback components must be connected as close to the device as possible. d l c s r s
RT8251 14 ds8251-04 february 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 10. pcb layout guide for psop-8 package v in v out gnd c in gnd c p c c r c sw d v out c out l r1 r2 input capacitor must be placed as close to the ic as possible. sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace. the feedback components must be connected as close to the device as possible. boot vin sw gnd ss en fb comp gnd 2 3 4 5 6 7 8 9 c ss r s c s gnd c boot table 3. suggested capacitors for c in and c out component supplier part no. v rr m (v) i out (a) package diodes b540c 40 5 smc on mbr s540t3 40 5 smc table 4. suggested diode location component supplier part no. capacitance ( f) case size c in murata grm31er61e226k 22 1210 c in tdk c4535x5r1e226m 22 1812 c in taiyo yuden tmk325bj226mm 22 1210 c out murata grm32er61c476m 47 1210 c out murata grm31cr60j476m 47 1206 c out tdk c3216x5r0j476m 47 1206 c out taiyo yuden lmk316bj476mm 47 1206
RT8251 15 ds8251-04 february 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. outline dimension a a1 a3 d e 1 d2 e2 l b e see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 1.300 1.750 0.051 0.069 e 2.950 3.050 0.116 0.120 e2 1.300 1.750 0.051 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 16l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2
RT8251 16 www.richtek.com ds8251-04 february 2013 richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138

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